1. Field of the Invention
This invention relates to an electronic apparatus comprising a semiconductor memory unit, and more particularly to an electronic apparatus in which contents of a semiconductor memory unit can be retained by supplying power from a backup power source even when the main power is lost.
2. Description of the Prior Art
In recent years, various types of portable electronic apparatus having a battery-driven microcomputer system which is miniaturized by advancements in LSI technology have found practical application. Furthermore, many of these electronic apparatus have a built-in battery for use as a battery backup to retain the stored contents of a semiconductor memory unit while the main power source battery is being replaced or when it has become worn out.
As a typical example of such an apparatus having a backup battery, a portable terminal apparatus which can be connected to a mainframe computer through a communication system is illustrated in FIG. 3. This apparatus comprises an LSI 1 in which a CPU and I/O interface unit are incorporated, a ROM 2, a RAM 3, a liquid crystal display unit 4, and a keyboard 5. The LSI 1, ROM 2, RAM 3 and liquid crystal display unit 4 are powered by a main battery 6. The RAM 3 is connected to the main battery 6 through a diode D.sub.1, and powered also by a backup battery 7 through a diode D.sub.2.
The chip select terminal CS (active low) of the RAM 3 is connected to the output port OUT of the LSI 1 via the selection control line 8. When the RAM 3 is to be accessed, a low level active signal is output from the output port OUT.
The selection control line 8 is raised to the level of the power source voltage V.sub.CC by a pull-up resistor R in order to prevent misoperation in the chip selection.
In the prior art apparatus, while the main battery 6 is being replaced or when it becomes worn out, the contents of the RAM 3 can be retained by the power supplied from the backup battery 7. In such a case, however, a bypass current flows to the output port OUT of the LSI 1 via the pull-up resistor R and the selection control line 8.
Therefore, in such an electronic apparatus of the prior art, unnecessary power is consumed by a sneak current flowing through the pull-up resistor R during the time the RAM 3 is powered by the backup battery 7. This causes the life of the backup battery 7 to be shortened, and thus the backup time by the battery 7 is considerably reduced.
FIG. 4 illustrates another portable terminal of the prior art. In the apparatus of FIG. 4, a backup battery 7 is connected to a voltage detection circuit 10 which comprises a detection IC 10A and a pull-down resistor 11. The voltage detection circuit 10 detects the output voltage of the backup battery 7, and its output level is inverted when the output voltage of the backup battery 7 falls below a predetermined threshold level. The output of the voltage detection circuit 10 is coupled to an input port IN of an LSI 1 through a level shift circuit 12 which shifts the output of the voltage detection circuit 10 to a level suitable for the input port IN.
A CPU in the LSI 1 periodically or intermittently monitors the output of level shift circuit 12 (i.e., the output of the detection circuit 10), using an interruption program or the like. When the CPU in the LSI 1 judges that the output voltage of the backup battery 7 has dropped below a fixed level, an alarm message is displayed on a display device (not shown in FIG. 4) to warn the user to replace the backup battery 7 with a new one. By this means, undesirable loss of data due to the lack of backup can be prevented from occurring.
In order for the detection circuit 10 to detect the voltage of the backup battery 7, however, current must pass the pull-down resistor 11. Therefore, the pull-down resistor 11 continuously consumes power. This causes the life of the backup battery 7 to be shortened, and thus the backup time by the battery 7 is considerably reduced.
As mentioned above, the voltage detected by the detection circuit 10 is not always monitored by the CPU in the LSI 1. Therefore, in such a prior art apparatus, the detection circuit 10 unnecessarily consumes power in periods of time other than when the voltage monitor operation is performed by the CPU in the LSI 1.